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planck_rev
Author | SHA1 | Date |
---|---|---|
Jack Humbert | 676080372c | 7 years ago |
Jack Humbert | 0af7415981 | 7 years ago |
Jack Humbert | df371458b3 | 7 years ago |
Jack Humbert | e0e5efbead | 7 years ago |
Jack Humbert | edb4460e64 | 7 years ago |
Jack Humbert | fe72bfa070 | 7 years ago |
Jack Humbert | 25642c8840 | 7 years ago |
Jack Humbert | 03b1904b2e | 7 years ago |
Jack Humbert | bb71a988c2 | 7 years ago |
Jack Humbert | ddee61c9ba | 7 years ago |
Jack Humbert | 91efe74365 | 7 years ago |
Jack Humbert | 12a64ff24b | 7 years ago |
@ -0,0 +1,556 @@
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/*
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WS2812B CPU and memory efficient library
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Date: 28.9.2016
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Author: Martin Hubacek
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http://www.martinhubacek.cz
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@hubmartin
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Licence: MIT License
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*/
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#include <string.h>
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#include "stm32f3xx_hal.h"
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#include "ws2812.h"
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extern WS2812_Struct ws2812b;
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// Define source arrays for my DMAs
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uint32_t WS2812_IO_High[] = { WS2812B_PINS };
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uint32_t WS2812_IO_Low[] = {WS2812B_PINS << 16};
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// WS2812 framebuffer - buffer for 2 LEDs - two times 24 bits
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uint16_t ws2812bDmaBitBuffer[24 * 2];
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// Gamma correction table
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const uint8_t gammaTable[] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
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2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5,
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5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10,
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10, 10, 11, 11, 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 16, 16,
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17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24, 24, 25,
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25, 26, 27, 27, 28, 29, 29, 30, 31, 32, 32, 33, 34, 35, 35, 36,
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37, 38, 39, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 50,
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51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 66, 67, 68,
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69, 70, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 85, 86, 87, 89,
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90, 92, 93, 95, 96, 98, 99,101,102,104,105,107,109,110,112,114,
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115,117,119,120,122,124,126,127,129,131,133,135,137,138,140,142,
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144,146,148,150,152,154,156,158,160,162,164,167,169,171,173,175,
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177,180,182,184,186,189,191,193,196,198,200,203,205,208,210,213,
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215,218,220,223,225,228,231,233,236,239,241,244,247,249,252,255 };
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static void ws2812b_gpio_init(void)
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{
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// WS2812B outputs
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WS2812B_GPIO_CLK_ENABLE();
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitStruct.Pin = WS2812B_PINS;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(WS2812B_PORT, &GPIO_InitStruct);
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// Enable output pins for debuging to see DMA Full and Half transfer interrupts
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#if defined(LED4_PORT) && defined(LED5_PORT)
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
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GPIO_InitStruct.Pin = LED4_PIN;
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HAL_GPIO_Init(LED4_PORT, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = LED5_PIN;
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HAL_GPIO_Init(LED5_PORT, &GPIO_InitStruct);
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#endif
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}
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TIM_HandleTypeDef Tim2Handle;
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TIM_OC_InitTypeDef tim2OC1;
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TIM_OC_InitTypeDef tim2OC2;
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uint32_t tim_period;
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static void TIM2_init(void)
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{
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// TIM2 Periph clock enable
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__HAL_RCC_TIM2_CLK_ENABLE();
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// This computation of pulse length should work ok,
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// at some slower core speeds it needs some tuning.
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tim_period = SystemCoreClock / 800000; // 0,125us period (10 times lower the 1,25us period to have fixed math below)
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uint32_t cc1 = (10 * tim_period) / 36;
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uint32_t cc2 = (10 * tim_period) / 15;
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Tim2Handle.Instance = TIM2;
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Tim2Handle.Init.Period = tim_period;
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Tim2Handle.Init.RepetitionCounter = 0;
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Tim2Handle.Init.Prescaler = 0;
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Tim2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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Tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
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HAL_TIM_PWM_Init(&Tim2Handle);
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HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(TIM2_IRQn);
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tim2OC1.OCMode = TIM_OCMODE_PWM1;
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tim2OC1.OCPolarity = TIM_OCPOLARITY_HIGH;
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tim2OC1.Pulse = cc1;
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tim2OC1.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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tim2OC1.OCFastMode = TIM_OCFAST_DISABLE;
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HAL_TIM_PWM_ConfigChannel(&Tim2Handle, &tim2OC1, TIM_CHANNEL_1);
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tim2OC2.OCMode = TIM_OCMODE_PWM1;
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tim2OC2.OCPolarity = TIM_OCPOLARITY_HIGH;
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tim2OC2.Pulse = cc2;
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tim2OC2.OCNPolarity = TIM_OCNPOLARITY_HIGH;
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tim2OC2.OCFastMode = TIM_OCFAST_DISABLE;
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tim2OC2.OCIdleState = TIM_OCIDLESTATE_RESET;
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tim2OC2.OCNIdleState = TIM_OCNIDLESTATE_RESET;
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HAL_TIM_PWM_ConfigChannel(&Tim2Handle, &tim2OC2, TIM_CHANNEL_2);
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HAL_TIM_Base_Start(&Tim2Handle);
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HAL_TIM_PWM_Start(&Tim2Handle, TIM_CHANNEL_1);
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}
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DMA_HandleTypeDef dmaUpdate;
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DMA_HandleTypeDef dmaCC1;
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DMA_HandleTypeDef dmaCC2;
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#define BUFFER_SIZE (sizeof(ws2812bDmaBitBuffer)/sizeof(uint16_t))
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static void DMA_init(void)
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{
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// TIM2 Update event
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__HAL_RCC_DMA1_CLK_ENABLE();
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dmaUpdate.Init.Direction = DMA_MEMORY_TO_PERIPH;
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dmaUpdate.Init.PeriphInc = DMA_PINC_DISABLE;
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dmaUpdate.Init.MemInc = DMA_MINC_DISABLE;
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dmaUpdate.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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dmaUpdate.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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dmaUpdate.Init.Mode = DMA_CIRCULAR;
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dmaUpdate.Init.Priority = DMA_PRIORITY_VERY_HIGH;
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dmaUpdate.Instance = DMA1_Channel2;
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//dmaUpdate.XferCpltCallback = TransferComplete;
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//dmaUpdate.XferErrorCallback = TransferError;
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HAL_DMA_Init(&dmaUpdate);
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//HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
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//HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
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HAL_DMA_Start(&dmaUpdate, (uint32_t)WS2812_IO_High, (uint32_t)&WS2812B_PORT->BSRR, BUFFER_SIZE);
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// TIM2 CC1 event
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dmaCC1.Init.Direction = DMA_MEMORY_TO_PERIPH;
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dmaCC1.Init.PeriphInc = DMA_PINC_DISABLE;
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dmaCC1.Init.MemInc = DMA_MINC_ENABLE;
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dmaCC1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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dmaCC1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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dmaCC1.Init.Mode = DMA_CIRCULAR;
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dmaCC1.Init.Priority = DMA_PRIORITY_VERY_HIGH;
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dmaCC1.Instance = DMA1_Channel5;
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//dmaUpdate.XferCpltCallback = TransferComplete;
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//dmaUpdate.XferErrorCallback = TransferError;
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//dmaUpdate.XferHalfCpltCallback = TransferHalf;
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//HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
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//HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
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HAL_DMA_Init(&dmaCC1);
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HAL_DMA_Start(&dmaCC1, (uint32_t)ws2812bDmaBitBuffer, (uint32_t)&WS2812B_PORT->BRR, BUFFER_SIZE);
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// TIM2 CC2 event
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dmaCC2.Init.Direction = DMA_MEMORY_TO_PERIPH;
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dmaCC2.Init.PeriphInc = DMA_PINC_DISABLE;
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dmaCC2.Init.MemInc = DMA_MINC_DISABLE;
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dmaCC2.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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dmaCC2.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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dmaCC2.Init.Mode = DMA_CIRCULAR;
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dmaCC2.Init.Priority = DMA_PRIORITY_VERY_HIGH;
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dmaCC2.Instance = DMA1_Channel7;
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dmaCC2.XferCpltCallback = DMA_TransferCompleteHandler;
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dmaCC2.XferHalfCpltCallback = DMA_TransferHalfHandler;
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//dmaUpdate.XferErrorCallback = TransferError;
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HAL_DMA_Init(&dmaCC2);
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HAL_NVIC_SetPriority(DMA1_Channel7_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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HAL_DMA_Start_IT(&dmaCC2, (uint32_t)WS2812_IO_Low, (uint32_t)&WS2812B_PORT->BSRR, BUFFER_SIZE);
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}
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/*
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void DMA1_Channel2_IRQHandler(void)
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{
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// Check the interrupt and clear flag
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HAL_DMA_IRQHandler(&dmaUpdate);
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}
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void DMA1_Channel5_IRQHandler(void)
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{
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// Check the interrupt and clear flag
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HAL_DMA_IRQHandler(&dmaCC1);
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}*/
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void DMA1_Channel7_IRQHandler(void)
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{
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// Check the interrupt and clear flag
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HAL_DMA_IRQHandler(&dmaCC2);
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}
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static void loadNextFramebufferData(WS2812_BufferItem *bItem, uint32_t row)
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{
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uint32_t r = bItem->frameBufferPointer[bItem->frameBufferCounter++];
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uint32_t g = bItem->frameBufferPointer[bItem->frameBufferCounter++];
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uint32_t b = bItem->frameBufferPointer[bItem->frameBufferCounter++];
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if(bItem->frameBufferCounter == bItem->frameBufferSize)
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bItem->frameBufferCounter = 0;
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ws2812b_set_pixel(bItem->channel, row, r, g, b);
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}
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// Transmit the framebuffer
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static void WS2812_sendbuf()
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{
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// transmission complete flag
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ws2812b.transferComplete = 0;
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uint32_t i;
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for( i = 0; i < WS2812_BUFFER_COUNT; i++ )
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{
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ws2812b.item[i].frameBufferCounter = 0;
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loadNextFramebufferData(&ws2812b.item[i], 0); // ROW 0
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loadNextFramebufferData(&ws2812b.item[i], 1); // ROW 0
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}
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// clear all DMA flags
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__HAL_DMA_CLEAR_FLAG(&dmaUpdate, DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2);
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__HAL_DMA_CLEAR_FLAG(&dmaCC1, DMA_FLAG_TC5 | DMA_FLAG_HT5 | DMA_FLAG_TE5);
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__HAL_DMA_CLEAR_FLAG(&dmaCC2, DMA_FLAG_TC7 | DMA_FLAG_HT7 | DMA_FLAG_TE7);
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// configure the number of bytes to be transferred by the DMA controller
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dmaUpdate.Instance->CNDTR = BUFFER_SIZE;
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dmaCC1.Instance->CNDTR = BUFFER_SIZE;
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dmaCC2.Instance->CNDTR = BUFFER_SIZE;
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// clear all TIM2 flags
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__HAL_TIM_CLEAR_FLAG(&Tim2Handle, TIM_FLAG_UPDATE | TIM_FLAG_CC1 | TIM_FLAG_CC2 | TIM_FLAG_CC3 | TIM_FLAG_CC4);
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// enable DMA channels
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__HAL_DMA_ENABLE(&dmaUpdate);
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__HAL_DMA_ENABLE(&dmaCC1);
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__HAL_DMA_ENABLE(&dmaCC2);
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// IMPORTANT: enable the TIM2 DMA requests AFTER enabling the DMA channels!
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__HAL_TIM_ENABLE_DMA(&Tim2Handle, TIM_DMA_UPDATE);
|
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__HAL_TIM_ENABLE_DMA(&Tim2Handle, TIM_DMA_CC1);
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__HAL_TIM_ENABLE_DMA(&Tim2Handle, TIM_DMA_CC2);
|
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|
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TIM2->CNT = tim_period-1;
|
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|
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// start TIM2
|
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__HAL_TIM_ENABLE(&Tim2Handle);
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||||||
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}
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|
||||||
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|
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|
||||||
|
|
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|
void DMA_TransferHalfHandler(DMA_HandleTypeDef *DmaHandle)
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|
{
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|
#if defined(LED4_PORT)
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LED4_PORT->BSRR = LED4_PIN;
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|
#endif
|
||||||
|
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|
// Is this the last LED?
|
||||||
|
if(ws2812b.repeatCounter != (WS2812B_NUMBER_OF_LEDS / 2 - 1))
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for( i = 0; i < WS2812_BUFFER_COUNT; i++ )
|
||||||
|
{
|
||||||
|
loadNextFramebufferData(&ws2812b.item[i], 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
} else {
|
||||||
|
// If this is the last pixel, set the next pixel value to zeros, because
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||||||
|
// the DMA would not stop exactly at the last bit.
|
||||||
|
ws2812b_set_pixel(0, 0, 0, 0, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(LED4_PORT)
|
||||||
|
LED4_PORT->BRR = LED4_PIN;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
void DMA_TransferCompleteHandler(DMA_HandleTypeDef *DmaHandle)
|
||||||
|
{
|
||||||
|
#if defined(LED5_PORT)
|
||||||
|
LED5_PORT->BSRR = LED5_PIN;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ws2812b.repeatCounter++;
|
||||||
|
|
||||||
|
if(ws2812b.repeatCounter == WS2812B_NUMBER_OF_LEDS / 2)
|
||||||
|
{
|
||||||
|
// Transfer of all LEDs is done, disable DMA but enable tiemr update IRQ to stop the 50us pulse
|
||||||
|
ws2812b.repeatCounter = 0;
|
||||||
|
|
||||||
|
// Enable TIM2 Update interrupt for 50us Treset signal
|
||||||
|
__HAL_TIM_ENABLE_IT(&Tim2Handle, TIM_IT_UPDATE);
|
||||||
|
// Disable DMA
|
||||||
|
__HAL_DMA_DISABLE(&dmaUpdate);
|
||||||
|
__HAL_DMA_DISABLE(&dmaCC1);
|
||||||
|
__HAL_DMA_DISABLE(&dmaCC2);
|
||||||
|
|
||||||
|
// Disable the DMA requests
|
||||||
|
__HAL_TIM_DISABLE_DMA(&Tim2Handle, TIM_DMA_UPDATE);
|
||||||
|
__HAL_TIM_DISABLE_DMA(&Tim2Handle, TIM_DMA_CC1);
|
||||||
|
__HAL_TIM_DISABLE_DMA(&Tim2Handle, TIM_DMA_CC2);
|
||||||
|
|
||||||
|
// Manually set outputs to low to generate 50us reset impulse
|
||||||
|
WS2812B_PORT->BSRR = WS2812_IO_Low[0];
|
||||||
|
} else {
|
||||||
|
|
||||||
|
// Load bitbuffer with next RGB LED values
|
||||||
|
uint32_t i;
|
||||||
|
for( i = 0; i < WS2812_BUFFER_COUNT; i++ )
|
||||||
|
{
|
||||||
|
loadNextFramebufferData(&ws2812b.item[i], 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(LED5_PORT)
|
||||||
|
LED5_PORT->BRR = LED5_PIN;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void TIM2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
HAL_TIM_IRQHandler(&Tim2Handle);
|
||||||
|
}
|
||||||
|
|
||||||
|
// TIM2 Interrupt Handler gets executed on every TIM2 Update if enabled
|
||||||
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||||
|
{
|
||||||
|
// I have to wait 50us to generate Treset signal
|
||||||
|
if (ws2812b.timerPeriodCounter < (uint8_t)WS2812_RESET_PERIOD)
|
||||||
|
{
|
||||||
|
// count the number of timer periods
|
||||||
|
ws2812b.timerPeriodCounter++;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ws2812b.timerPeriodCounter = 0;
|
||||||
|
__HAL_TIM_DISABLE(&Tim2Handle);
|
||||||
|
TIM2->CR1 = 0; // disable timer
|
||||||
|
|
||||||
|
// disable the TIM2 Update
|
||||||
|
__HAL_TIM_DISABLE_IT(&Tim2Handle, TIM_IT_UPDATE);
|
||||||
|
// set TransferComplete flag
|
||||||
|
ws2812b.transferComplete = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
static void ws2812b_set_pixel(uint8_t row, uint16_t column, uint8_t red, uint8_t green, uint8_t blue)
|
||||||
|
{
|
||||||
|
|
||||||
|
// Apply gamma
|
||||||
|
red = gammaTable[red];
|
||||||
|
green = gammaTable[green];
|
||||||
|
blue = gammaTable[blue];
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t calcCol = (column*24);
|
||||||
|
uint32_t invRed = ~red;
|
||||||
|
uint32_t invGreen = ~green;
|
||||||
|
uint32_t invBlue = ~blue;
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(SETPIX_1)
|
||||||
|
uint8_t i;
|
||||||
|
uint32_t calcClearRow = ~(0x01<<row);
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
// clear the data for pixel
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+i)] &= calcClearRow;
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+i)] &= calcClearRow;
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+i)] &= calcClearRow;
|
||||||
|
|
||||||
|
// write new data for pixel
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+i)] |= (((((invGreen)<<i) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+i)] |= (((((invRed)<<i) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+i)] |= (((((invBlue)<<i) & 0x80)>>7)<<row);
|
||||||
|
}
|
||||||
|
#elif defined(SETPIX_2)
|
||||||
|
uint8_t i;
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
{
|
||||||
|
// Set or clear the data for the pixel
|
||||||
|
|
||||||
|
if(((invGreen)<<i) & 0x80)
|
||||||
|
varSetBit(ws2812bDmaBitBuffer[(calcCol+i)], row);
|
||||||
|
else
|
||||||
|
varResetBit(ws2812bDmaBitBuffer[(calcCol+i)], row);
|
||||||
|
|
||||||
|
if(((invRed)<<i) & 0x80)
|
||||||
|
varSetBit(ws2812bDmaBitBuffer[(calcCol+8+i)], row);
|
||||||
|
else
|
||||||
|
varResetBit(ws2812bDmaBitBuffer[(calcCol+8+i)], row);
|
||||||
|
|
||||||
|
if(((invBlue)<<i) & 0x80)
|
||||||
|
varSetBit(ws2812bDmaBitBuffer[(calcCol+16+i)], row);
|
||||||
|
else
|
||||||
|
varResetBit(ws2812bDmaBitBuffer[(calcCol+16+i)], row);
|
||||||
|
|
||||||
|
}
|
||||||
|
#elif defined(SETPIX_3)
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+0)] |= (((((invGreen)<<0) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+0)] |= (((((invRed)<<0) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+0)] |= (((((invBlue)<<0) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+1)] |= (((((invGreen)<<1) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+1)] |= (((((invRed)<<1) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+1)] |= (((((invBlue)<<1) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+2)] |= (((((invGreen)<<2) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+2)] |= (((((invRed)<<2) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+2)] |= (((((invBlue)<<2) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+3)] |= (((((invGreen)<<3) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+3)] |= (((((invRed)<<3) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+3)] |= (((((invBlue)<<3) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+4)] |= (((((invGreen)<<4) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+4)] |= (((((invRed)<<4) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+4)] |= (((((invBlue)<<4) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+5)] |= (((((invGreen)<<5) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+5)] |= (((((invRed)<<5) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+5)] |= (((((invBlue)<<5) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+6)] |= (((((invGreen)<<6) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+6)] |= (((((invRed)<<6) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+6)] |= (((((invBlue)<<6) & 0x80)>>7)<<row);
|
||||||
|
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+7)] |= (((((invGreen)<<7) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+8+7)] |= (((((invRed)<<7) & 0x80)>>7)<<row);
|
||||||
|
ws2812bDmaBitBuffer[(calcCol+16+7)] |= (((((invBlue)<<7) & 0x80)>>7)<<row);
|
||||||
|
#elif defined(SETPIX_4)
|
||||||
|
|
||||||
|
// Bitband optimizations with pure increments, 5us interrupts
|
||||||
|
uint32_t *bitBand = BITBAND_SRAM(&ws2812bDmaBitBuffer[(calcCol)], row);
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 7);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 6);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 5);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 4);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 3);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 2);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 1);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invGreen >> 0);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
// RED
|
||||||
|
*bitBand = (invRed >> 7);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 6);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 5);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 4);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 3);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 2);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 1);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invRed >> 0);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
// BLUE
|
||||||
|
*bitBand = (invBlue >> 7);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 6);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 5);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 4);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 3);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 2);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 1);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
*bitBand = (invBlue >> 0);
|
||||||
|
bitBand+=16;
|
||||||
|
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void ws2812b_init()
|
||||||
|
{
|
||||||
|
ws2812b_gpio_init();
|
||||||
|
DMA_init();
|
||||||
|
TIM2_init();
|
||||||
|
|
||||||
|
// Need to start the first transfer
|
||||||
|
ws2812b.transferComplete = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void ws2812b_handle()
|
||||||
|
{
|
||||||
|
if(ws2812b.startTransfer) {
|
||||||
|
ws2812b.startTransfer = 0;
|
||||||
|
WS2812_sendbuf();
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
@ -0,0 +1,94 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
WS2812B CPU and memory efficient library
|
||||||
|
|
||||||
|
Date: 28.9.2016
|
||||||
|
|
||||||
|
Author: Martin Hubacek
|
||||||
|
http://www.martinhubacek.cz
|
||||||
|
@hubmartin
|
||||||
|
|
||||||
|
Licence: MIT License
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef WS2812B_H_
|
||||||
|
#define WS2812B_H_
|
||||||
|
#include "ws2812.h"
|
||||||
|
|
||||||
|
// GPIO enable command
|
||||||
|
#define WS2812B_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||||
|
// LED output port
|
||||||
|
#define WS2812B_PORT GPIOC
|
||||||
|
// LED output pins
|
||||||
|
#define WS2812B_PINS (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3)
|
||||||
|
// How many LEDs are in the series
|
||||||
|
#define WS2812B_NUMBER_OF_LEDS 60
|
||||||
|
|
||||||
|
// Number of output LED strips. Each has its own buffer.
|
||||||
|
#define WS2812_BUFFER_COUNT 2
|
||||||
|
|
||||||
|
// Choose one of the bit-juggling setpixel implementation
|
||||||
|
// *******************************************************
|
||||||
|
//#define SETPIX_1 // For loop, works everywhere, slow
|
||||||
|
//#define SETPIX_2 // Bit band in a loop
|
||||||
|
//#define SETPIX_3 // Like SETPIX_1 but with unrolled loop
|
||||||
|
#define SETPIX_4 // Fastest copying using bit-banding
|
||||||
|
|
||||||
|
|
||||||
|
// DEBUG OUTPUT
|
||||||
|
// ********************
|
||||||
|
#define LED4_PORT GPIOC
|
||||||
|
#define LED4_PIN GPIO_PIN_10
|
||||||
|
|
||||||
|
#define LED5_PORT GPIOC
|
||||||
|
#define LED5_PIN GPIO_PIN_10
|
||||||
|
|
||||||
|
|
||||||
|
// Public functions
|
||||||
|
// ****************
|
||||||
|
void ws2812b_init();
|
||||||
|
void ws2812b_handle();
|
||||||
|
|
||||||
|
// Library structures
|
||||||
|
// ******************
|
||||||
|
// This value sets number of periods to generate 50uS Treset signal
|
||||||
|
#define WS2812_RESET_PERIOD 12
|
||||||
|
|
||||||
|
typedef struct WS2812_BufferItem {
|
||||||
|
uint8_t* frameBufferPointer;
|
||||||
|
uint32_t frameBufferSize;
|
||||||
|
uint32_t frameBufferCounter;
|
||||||
|
uint8_t channel; // digital output pin/channel
|
||||||
|
} WS2812_BufferItem;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct WS2812_Struct
|
||||||
|
{
|
||||||
|
WS2812_BufferItem item[WS2812_BUFFER_COUNT];
|
||||||
|
uint8_t transferComplete;
|
||||||
|
uint8_t startTransfer;
|
||||||
|
uint32_t timerPeriodCounter;
|
||||||
|
uint32_t repeatCounter;
|
||||||
|
} WS2812_Struct;
|
||||||
|
|
||||||
|
WS2812_Struct ws2812b;
|
||||||
|
|
||||||
|
// Bit band stuff
|
||||||
|
#define RAM_BASE 0x20000000
|
||||||
|
#define RAM_BB_BASE 0x22000000
|
||||||
|
#define Var_ResetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 0)
|
||||||
|
#define Var_SetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)) = 1)
|
||||||
|
#define Var_GetBit_BB(VarAddr, BitNumber) (*(volatile uint32_t *) (RAM_BB_BASE | ((VarAddr - RAM_BASE) << 5) | ((BitNumber) << 2)))
|
||||||
|
#define BITBAND_SRAM(address, bit) ( (__IO uint32_t *) (RAM_BB_BASE + (((uint32_t)address) - RAM_BASE) * 32 + (bit) * 4))
|
||||||
|
|
||||||
|
#define varSetBit(var,bit) (Var_SetBit_BB((uint32_t)&var,bit))
|
||||||
|
#define varResetBit(var,bit) (Var_ResetBit_BB((uint32_t)&var,bit))
|
||||||
|
#define varGetBit(var,bit) (Var_GetBit_BB((uint32_t)&var,bit))
|
||||||
|
|
||||||
|
static void ws2812b_set_pixel(uint8_t row, uint16_t column, uint8_t red, uint8_t green, uint8_t blue);
|
||||||
|
void DMA_TransferCompleteHandler(DMA_HandleTypeDef *DmaHandle);
|
||||||
|
void DMA_TransferHalfHandler(DMA_HandleTypeDef *DmaHandle);
|
||||||
|
|
||||||
|
#endif /* WS2812B_H_ */
|
@ -0,0 +1 @@
|
|||||||
|
SRC += muse.c
|
@ -0,0 +1,126 @@
|
|||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "hal.h"
|
||||||
|
|
||||||
|
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief PAL setup.
|
||||||
|
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||||
|
* This variable is used by the HAL when initializing the PAL driver.
|
||||||
|
*/
|
||||||
|
const PALConfig pal_default_config = {
|
||||||
|
#if STM32_HAS_GPIOA
|
||||||
|
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||||
|
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOB
|
||||||
|
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||||
|
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOC
|
||||||
|
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||||
|
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOD
|
||||||
|
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||||
|
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOE
|
||||||
|
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||||
|
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOF
|
||||||
|
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||||
|
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOG
|
||||||
|
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||||
|
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOH
|
||||||
|
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||||
|
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||||
|
#endif
|
||||||
|
#if STM32_HAS_GPIOI
|
||||||
|
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||||
|
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void enter_bootloader_mode_if_requested(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Early initialization code.
|
||||||
|
* @details This initialization must be performed just after stack setup
|
||||||
|
* and before any other initialization.
|
||||||
|
*/
|
||||||
|
void __early_init(void) {
|
||||||
|
enter_bootloader_mode_if_requested();
|
||||||
|
stm32_clock_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief SDC card detection.
|
||||||
|
*/
|
||||||
|
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||||
|
|
||||||
|
(void)sdcp;
|
||||||
|
/* TODO: Fill the implementation.*/
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SDC card write protection detection.
|
||||||
|
*/
|
||||||
|
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||||
|
|
||||||
|
(void)sdcp;
|
||||||
|
/* TODO: Fill the implementation.*/
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
#endif /* HAL_USE_SDC */
|
||||||
|
|
||||||
|
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||||
|
/**
|
||||||
|
* @brief MMC_SPI card detection.
|
||||||
|
*/
|
||||||
|
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||||
|
|
||||||
|
(void)mmcp;
|
||||||
|
/* TODO: Fill the implementation.*/
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief MMC_SPI card write protection detection.
|
||||||
|
*/
|
||||||
|
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||||
|
|
||||||
|
(void)mmcp;
|
||||||
|
/* TODO: Fill the implementation.*/
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Board-specific initialization code.
|
||||||
|
* @todo Add your board-specific code, if any.
|
||||||
|
*/
|
||||||
|
void boardInit(void) {
|
||||||
|
}
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,5 @@
|
|||||||
|
# List of all the board related files.
|
||||||
|
BOARDSRC = $(BOARD_PATH)/boards/GENERIC_STM32_F303XC/board.c
|
||||||
|
|
||||||
|
# Required include directories
|
||||||
|
BOARDINC = $(BOARD_PATH)/boards/GENERIC_STM32_F303XC
|
@ -0,0 +1,7 @@
|
|||||||
|
/* Address for jumping to bootloader on STM32 chips. */
|
||||||
|
/* It is chip dependent, the correct number can be looked up here:
|
||||||
|
* http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
|
||||||
|
* This also requires a patch to chibios:
|
||||||
|
* <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
|
||||||
|
*/
|
||||||
|
#define STM32_BOOTLOADER_ADDRESS 0x1FFFD800
|
@ -0,0 +1,520 @@
|
|||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file templates/chconf.h
|
||||||
|
* @brief Configuration file template.
|
||||||
|
* @details A copy of this file must be placed in each project directory, it
|
||||||
|
* contains the application specific kernel settings.
|
||||||
|
*
|
||||||
|
* @addtogroup config
|
||||||
|
* @details Kernel related settings and hooks.
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CHCONF_H
|
||||||
|
#define CHCONF_H
|
||||||
|
|
||||||
|
#define _CHIBIOS_RT_CONF_
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name System timers settings
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System time counter resolution.
|
||||||
|
* @note Allowed values are 16 or 32 bits.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_ST_RESOLUTION 32
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System tick frequency.
|
||||||
|
* @details Frequency of the system timer that drives the system ticks. This
|
||||||
|
* setting also defines the system tick time unit.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_ST_FREQUENCY 10000
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Time delta constant for the tick-less mode.
|
||||||
|
* @note If this value is zero then the system uses the classic
|
||||||
|
* periodic tick. This value represents the minimum number
|
||||||
|
* of ticks that is safe to specify in a timeout directive.
|
||||||
|
* The value one is not valid, timeouts are rounded up to
|
||||||
|
* this value.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_ST_TIMEDELTA 2
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Kernel parameters and options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Round robin interval.
|
||||||
|
* @details This constant is the number of system ticks allowed for the
|
||||||
|
* threads before preemption occurs. Setting this value to zero
|
||||||
|
* disables the preemption for threads with equal priority and the
|
||||||
|
* round robin becomes cooperative. Note that higher priority
|
||||||
|
* threads can still preempt, the kernel is always preemptive.
|
||||||
|
* @note Disabling the round robin preemption makes the kernel more compact
|
||||||
|
* and generally faster.
|
||||||
|
* @note The round robin preemption is not supported in tickless mode and
|
||||||
|
* must be set to zero in that case.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_TIME_QUANTUM 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Managed RAM size.
|
||||||
|
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||||
|
* then the whole available RAM is used. The core memory is made
|
||||||
|
* available to the heap allocator and/or can be used directly through
|
||||||
|
* the simplified core memory allocator.
|
||||||
|
*
|
||||||
|
* @note In order to let the OS manage the whole RAM the linker script must
|
||||||
|
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||||
|
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_MEMCORE_SIZE 0
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Idle thread automatic spawn suppression.
|
||||||
|
* @details When this option is activated the function @p chSysInit()
|
||||||
|
* does not spawn the idle thread. The application @p main()
|
||||||
|
* function becomes the idle thread and must implement an
|
||||||
|
* infinite loop.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_NO_IDLE_THREAD FALSE
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Performance options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief OS optimization.
|
||||||
|
* @details If enabled then time efficient rather than space efficient code
|
||||||
|
* is used when two possible implementations exist.
|
||||||
|
*
|
||||||
|
* @note This is not related to the compiler optimization options.
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_OPTIMIZE_SPEED TRUE
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Subsystem options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Time Measurement APIs.
|
||||||
|
* @details If enabled then the time measurement APIs are included in
|
||||||
|
* the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_TM TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Threads registry APIs.
|
||||||
|
* @details If enabled then the registry APIs are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_REGISTRY TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Threads synchronization APIs.
|
||||||
|
* @details If enabled then the @p chThdWait() function is included in
|
||||||
|
* the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_WAITEXIT TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Semaphores APIs.
|
||||||
|
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_SEMAPHORES TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Semaphores queuing mode.
|
||||||
|
* @details If enabled then the threads are enqueued on semaphores by
|
||||||
|
* priority rather than in FIFO order.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE. Enable this if you have special
|
||||||
|
* requirements.
|
||||||
|
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Mutexes APIs.
|
||||||
|
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MUTEXES TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables recursive behavior on mutexes.
|
||||||
|
* @note Recursive mutexes are heavier and have an increased
|
||||||
|
* memory footprint.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conditional Variables APIs.
|
||||||
|
* @details If enabled then the conditional variables APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_CONDVARS TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Conditional Variables APIs with timeout.
|
||||||
|
* @details If enabled then the conditional variables APIs with timeout
|
||||||
|
* specification are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_CONDVARS.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Events Flags APIs.
|
||||||
|
* @details If enabled then the event flags APIs are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_EVENTS TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Events Flags APIs with timeout.
|
||||||
|
* @details If enabled then the events APIs with timeout specification
|
||||||
|
* are included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_EVENTS.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Synchronous Messages APIs.
|
||||||
|
* @details If enabled then the synchronous messages APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MESSAGES TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Synchronous Messages queuing mode.
|
||||||
|
* @details If enabled then messages are served by priority rather than in
|
||||||
|
* FIFO order.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE. Enable this if you have special
|
||||||
|
* requirements.
|
||||||
|
* @note Requires @p CH_CFG_USE_MESSAGES.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MESSAGES_PRIORITY TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Mailboxes APIs.
|
||||||
|
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||||
|
* included in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MAILBOXES TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Core Memory Manager APIs.
|
||||||
|
* @details If enabled then the core memory manager APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MEMCORE TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Heap Allocator APIs.
|
||||||
|
* @details If enabled then the memory heap allocator APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
|
||||||
|
* @p CH_CFG_USE_SEMAPHORES.
|
||||||
|
* @note Mutexes are recommended.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_HEAP TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Memory Pools Allocator APIs.
|
||||||
|
* @details If enabled then the memory pools allocator APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_MEMPOOLS TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Dynamic Threads APIs.
|
||||||
|
* @details If enabled then the dynamic threads creation APIs are included
|
||||||
|
* in the kernel.
|
||||||
|
*
|
||||||
|
* @note The default is @p TRUE.
|
||||||
|
* @note Requires @p CH_CFG_USE_WAITEXIT.
|
||||||
|
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_USE_DYNAMIC TRUE
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Debug options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, kernel statistics.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_STATISTICS FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, system state check.
|
||||||
|
* @details If enabled the correct call protocol for system APIs is checked
|
||||||
|
* at runtime.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, parameters checks.
|
||||||
|
* @details If enabled then the checks on the API functions input
|
||||||
|
* parameters are activated.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_ENABLE_CHECKS FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, consistency checks.
|
||||||
|
* @details If enabled then all the assertions in the kernel code are
|
||||||
|
* activated. This includes consistency checks inside the kernel,
|
||||||
|
* runtime anomalies and port-defined checks.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_ENABLE_ASSERTS FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, trace buffer.
|
||||||
|
* @details If enabled then the trace buffer is activated.
|
||||||
|
*
|
||||||
|
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trace buffer entries.
|
||||||
|
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||||
|
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_TRACE_BUFFER_SIZE 128
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, stack checks.
|
||||||
|
* @details If enabled then a runtime stack check is performed.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
* @note The stack check is performed in a architecture/port dependent way.
|
||||||
|
* It may not be implemented or some ports.
|
||||||
|
* @note The default failure mode is to halt the system with the global
|
||||||
|
* @p panic_msg variable set to @p NULL.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_ENABLE_STACK_CHECK TRUE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, stacks initialization.
|
||||||
|
* @details If enabled then the threads working area is filled with a byte
|
||||||
|
* value when a thread is created. This can be useful for the
|
||||||
|
* runtime measurement of the used stack.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_FILL_THREADS FALSE
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Debug option, threads profiling.
|
||||||
|
* @details If enabled then a field is added to the @p thread_t structure that
|
||||||
|
* counts the system ticks occurred while executing the thread.
|
||||||
|
*
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
* @note This debug option is not currently compatible with the
|
||||||
|
* tickless mode.
|
||||||
|
*/
|
||||||
|
#define CH_DBG_THREADS_PROFILING FALSE
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/**
|
||||||
|
* @name Kernel hooks
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Threads descriptor structure extension.
|
||||||
|
* @details User fields added to the end of the @p thread_t structure.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_THREAD_EXTRA_FIELDS \
|
||||||
|
/* Add threads custom fields here.*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Threads initialization hook.
|
||||||
|
* @details User initialization code added to the @p chThdInit() API.
|
||||||
|
*
|
||||||
|
* @note It is invoked from within @p chThdInit() and implicitly from all
|
||||||
|
* the threads creation APIs.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||||
|
/* Add threads initialization code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Threads finalization hook.
|
||||||
|
* @details User finalization code added to the @p chThdExit() API.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||||
|
/* Add threads finalization code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Context switch hook.
|
||||||
|
* @details This hook is invoked just before switching between threads.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||||
|
/* Context switch code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ISR enter hook.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
|
||||||
|
/* IRQ prologue code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ISR exit hook.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
|
||||||
|
/* IRQ epilogue code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Idle thread enter hook.
|
||||||
|
* @note This hook is invoked within a critical zone, no OS functions
|
||||||
|
* should be invoked from here.
|
||||||
|
* @note This macro can be used to activate a power saving mode.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||||
|
/* Idle-enter code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Idle thread leave hook.
|
||||||
|
* @note This hook is invoked within a critical zone, no OS functions
|
||||||
|
* should be invoked from here.
|
||||||
|
* @note This macro can be used to deactivate a power saving mode.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||||
|
/* Idle-leave code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Idle Loop hook.
|
||||||
|
* @details This hook is continuously invoked by the idle thread loop.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_IDLE_LOOP_HOOK() { \
|
||||||
|
/* Idle loop code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System tick event hook.
|
||||||
|
* @details This hook is invoked in the system tick handler immediately
|
||||||
|
* after processing the virtual timers queue.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_SYSTEM_TICK_HOOK() { \
|
||||||
|
/* System tick event code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System halt hook.
|
||||||
|
* @details This hook is invoked in case to a system halting error before
|
||||||
|
* the system is halted.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||||
|
/* System halt code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trace hook.
|
||||||
|
* @details This hook is invoked each time a new record is written in the
|
||||||
|
* trace buffer.
|
||||||
|
*/
|
||||||
|
#define CH_CFG_TRACE_HOOK(tep) { \
|
||||||
|
/* Trace code here.*/ \
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#endif /* CHCONF_H */
|
||||||
|
|
||||||
|
/** @} */
|
@ -0,0 +1,128 @@
|
|||||||
|
/*
|
||||||
|
* Copyright 2018 Jack Humbert <jack.humb@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef REV6_CONFIG_H
|
||||||
|
#define REV6_CONFIG_H
|
||||||
|
|
||||||
|
/* USB Device descriptor parameter */
|
||||||
|
#define DEVICE_VER 0x0006
|
||||||
|
|
||||||
|
#undef MATRIX_ROWS
|
||||||
|
#undef MATRIX_COLS
|
||||||
|
/* key matrix size */
|
||||||
|
#define MATRIX_ROWS 8
|
||||||
|
#define MATRIX_COLS 6
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Keyboard Matrix Assignments
|
||||||
|
*
|
||||||
|
* Change this to how you wired your keyboard
|
||||||
|
* COLS: AVR pins used for columns, left to right
|
||||||
|
* ROWS: AVR pins used for rows, top to bottom
|
||||||
|
* DIODE_DIRECTION: COL2ROW = COL = Anode (+), ROW = Cathode (-, marked on diode)
|
||||||
|
* ROW2COL = ROW = Anode (+), COL = Cathode (-, marked on diode)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* Note: These are not used for arm boards. They're here purely as documentation.
|
||||||
|
* #define MATRIX_ROW_PINS { PB0, PB1, PB2, PA15, PA10 }
|
||||||
|
* #define MATRIX_COL_PINS { PA2, PA3, PA6, PB14, PB15, PA8, PA9, PA7, PB3, PB4, PC14, PC15, PC13, PB5, PB6 }
|
||||||
|
* #define UNUSED_PINS
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define MUSIC_MAP
|
||||||
|
#undef AUDIO_VOICES
|
||||||
|
#undef C6_AUDIO
|
||||||
|
|
||||||
|
/* Debounce reduces chatter (unintended double-presses) - set 0 if debouncing is not needed */
|
||||||
|
#define DEBOUNCE 6
|
||||||
|
|
||||||
|
/* Prevent modifiers from being stuck on after layer changes. */
|
||||||
|
#define PREVENT_STUCK_MODIFIERS
|
||||||
|
|
||||||
|
/* Mechanical locking support. Use KC_LCAP, KC_LNUM or KC_LSCR instead in keymap */
|
||||||
|
//#define LOCKING_SUPPORT_ENABLE
|
||||||
|
/* Locking resynchronize hack */
|
||||||
|
//#define LOCKING_RESYNC_ENABLE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Force NKRO
|
||||||
|
*
|
||||||
|
* Force NKRO (nKey Rollover) to be enabled by default, regardless of the saved
|
||||||
|
* state in the bootmagic EEPROM settings. (Note that NKRO must be enabled in the
|
||||||
|
* makefile for this to work.)
|
||||||
|
*
|
||||||
|
* If forced on, NKRO can be disabled via magic key (default = LShift+RShift+N)
|
||||||
|
* until the next keyboard reset.
|
||||||
|
*
|
||||||
|
* NKRO may prevent your keystrokes from being detected in the BIOS, but it is
|
||||||
|
* fully operational during normal computer usage.
|
||||||
|
*
|
||||||
|
* For a less heavy-handed approach, enable NKRO via magic key (LShift+RShift+N)
|
||||||
|
* or via bootmagic (hold SPACE+N while plugging in the keyboard). Once set by
|
||||||
|
* bootmagic, NKRO mode will always be enabled until it is toggled again during a
|
||||||
|
* power-up.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
//#define FORCE_NKRO
|
||||||
|
|
||||||
|
/* key combination for magic key command */
|
||||||
|
#define IS_COMMAND() ( \
|
||||||
|
keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) \
|
||||||
|
)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Feature disable options
|
||||||
|
* These options are also useful to firmware size reduction.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* disable debug print */
|
||||||
|
//#define NO_DEBUG
|
||||||
|
|
||||||
|
/* disable print */
|
||||||
|
//#define NO_PRINT
|
||||||
|
|
||||||
|
/* disable action features */
|
||||||
|
//#define NO_ACTION_LAYER
|
||||||
|
//#define NO_ACTION_TAPPING
|
||||||
|
//#define NO_ACTION_ONESHOT
|
||||||
|
//#define NO_ACTION_MACRO
|
||||||
|
//#define NO_ACTION_FUNCTION
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MIDI options
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Prevent use of disabled MIDI features in the keymap */
|
||||||
|
//#define MIDI_ENABLE_STRICT 1
|
||||||
|
|
||||||
|
/* enable basic MIDI features:
|
||||||
|
- MIDI notes can be sent when in Music mode is on
|
||||||
|
*/
|
||||||
|
//#define MIDI_BASIC
|
||||||
|
|
||||||
|
/* enable advanced MIDI features:
|
||||||
|
- MIDI notes can be added to the keymap
|
||||||
|
- Octave shift and transpose
|
||||||
|
- Virtual sustain, portamento, and modulation wheel
|
||||||
|
- etc.
|
||||||
|
*/
|
||||||
|
//#define MIDI_ADVANCED
|
||||||
|
|
||||||
|
/* override number of MIDI tone keycodes (each octave adds 12 keycodes and allocates 12 bytes) */
|
||||||
|
//#define MIDI_TONE_KEYCODE_OCTAVES 1
|
||||||
|
|
||||||
|
#endif
|
@ -0,0 +1,388 @@
|
|||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file templates/halconf.h
|
||||||
|
* @brief HAL configuration header.
|
||||||
|
* @details HAL configuration file, this file allows to enable or disable the
|
||||||
|
* various device drivers from your application. You may also use
|
||||||
|
* this file in order to override the device drivers default settings.
|
||||||
|
*
|
||||||
|
* @addtogroup HAL_CONF
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef HALCONF_H
|
||||||
|
#define HALCONF_H
|
||||||
|
|
||||||
|
#include "mcuconf.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the PAL subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_PAL TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the ADC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_ADC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the CAN subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_CAN FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the DAC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_DAC TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the EXT subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_EXT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the GPT subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_GPT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the I2C subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_I2C FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the I2S subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_I2S FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the ICU subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_ICU FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the MAC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_MAC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the MMC_SPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_MMC_SPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the PWM subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_PWM FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the QSPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_QSPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the RTC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_RTC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SDC subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SDC FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SERIAL subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SERIAL FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SERIAL over USB subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SERIAL_USB TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the SPI subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_SPI FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the UART subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_UART FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the USB subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_USB TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the WDG subsystem.
|
||||||
|
*/
|
||||||
|
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||||
|
#define HAL_USE_WDG FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* ADC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define ADC_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define ADC_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* CAN driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sleep mode related APIs inclusion switch.
|
||||||
|
*/
|
||||||
|
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||||
|
#define CAN_USE_SLEEP_MODE TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* I2C driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||||
|
*/
|
||||||
|
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define I2C_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* MAC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables an event sources for incoming packets.
|
||||||
|
*/
|
||||||
|
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||||
|
#define MAC_USE_ZERO_COPY FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables an event sources for incoming packets.
|
||||||
|
*/
|
||||||
|
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||||
|
#define MAC_USE_EVENTS TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* MMC_SPI driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Delays insertions.
|
||||||
|
* @details If enabled this options inserts delays into the MMC waiting
|
||||||
|
* routines releasing some extra CPU time for the threads with
|
||||||
|
* lower priority, this may slow down the driver a bit however.
|
||||||
|
* This option is recommended also if the SPI driver does not
|
||||||
|
* use a DMA channel and heavily loads the CPU.
|
||||||
|
*/
|
||||||
|
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||||
|
#define MMC_NICE_WAITING TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SDC driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Number of initialization attempts before rejecting the card.
|
||||||
|
* @note Attempts are performed at 10mS intervals.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_INIT_RETRY 100
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Include support for MMC cards.
|
||||||
|
* @note MMC support is not yet implemented so this option must be kept
|
||||||
|
* at @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_MMC_SUPPORT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Delays insertions.
|
||||||
|
* @details If enabled this options inserts delays into the MMC waiting
|
||||||
|
* routines releasing some extra CPU time for the threads with
|
||||||
|
* lower priority, this may slow down the driver a bit however.
|
||||||
|
*/
|
||||||
|
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||||
|
#define SDC_NICE_WAITING TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SERIAL driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Default bit rate.
|
||||||
|
* @details Configuration parameter, this is the baud rate selected for the
|
||||||
|
* default configuration.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_DEFAULT_BITRATE 38400
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial buffers size.
|
||||||
|
* @details Configuration parameter, you can change the depth of the queue
|
||||||
|
* buffers depending on the requirements of your application.
|
||||||
|
* @note The default is 16 bytes for both the transmission and receive
|
||||||
|
* buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_BUFFERS_SIZE 16
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SERIAL_USB driver related setting. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial over USB buffers size.
|
||||||
|
* @details Configuration parameter, the buffer size must be a multiple of
|
||||||
|
* the USB data endpoint maximum packet size.
|
||||||
|
* @note The default is 256 bytes for both the transmission and receive
|
||||||
|
* buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_USB_BUFFERS_SIZE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Serial over USB number of buffers.
|
||||||
|
* @note The default is 2 buffers.
|
||||||
|
*/
|
||||||
|
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||||
|
#define SERIAL_USB_BUFFERS_NUMBER 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* SPI driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define SPI_USE_MUTUAL_EXCLUSION TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* UART driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define UART_USE_WAIT FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||||
|
#define UART_USE_MUTUAL_EXCLUSION FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* USB driver related settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables synchronous APIs.
|
||||||
|
* @note Disabling this option saves both code and data space.
|
||||||
|
*/
|
||||||
|
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||||
|
#define USB_USE_WAIT TRUE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HALCONF_H */
|
||||||
|
|
||||||
|
/** @} */
|
@ -0,0 +1,205 @@
|
|||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include "hal.h"
|
||||||
|
#include "timer.h"
|
||||||
|
#include "wait.h"
|
||||||
|
#include "printf.h"
|
||||||
|
#include "backlight.h"
|
||||||
|
#include "matrix.h"
|
||||||
|
#include "action.h"
|
||||||
|
#include "keycode.h"
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* col: { B11, B10, B2, B1, A7, B0 }
|
||||||
|
* row: { A10, A9, A8, B15, C13, C14, C15, A2 }
|
||||||
|
*/
|
||||||
|
/* matrix state(1:on, 0:off) */
|
||||||
|
static matrix_row_t matrix[MATRIX_ROWS];
|
||||||
|
static matrix_row_t matrix_debouncing[MATRIX_COLS];
|
||||||
|
static bool debouncing = false;
|
||||||
|
static uint16_t debouncing_time = 0;
|
||||||
|
|
||||||
|
static uint8_t encoder_state = 0;
|
||||||
|
static int8_t encoder_value = 0;
|
||||||
|
static int8_t encoder_LUT[] = { 0, -1, 1, 0, 1, 0, 0, -1, -1, 0, 0, 1, 0, 1, -1, 0 };
|
||||||
|
|
||||||
|
static bool dip_switch[4] = {0, 0, 0, 0};
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void matrix_init_user(void) {}
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void matrix_scan_user(void) {}
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void matrix_init_kb(void) {
|
||||||
|
matrix_init_user();
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void matrix_scan_kb(void) {
|
||||||
|
matrix_scan_user();
|
||||||
|
}
|
||||||
|
|
||||||
|
void matrix_init(void) {
|
||||||
|
printf("matrix init\n");
|
||||||
|
//debug_matrix = true;
|
||||||
|
|
||||||
|
// dip switch setup
|
||||||
|
palSetPadMode(GPIOB, 14, PAL_MODE_INPUT_PULLUP);
|
||||||
|
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT_PULLUP);
|
||||||
|
palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLUP);
|
||||||
|
palSetPadMode(GPIOB, 9, PAL_MODE_INPUT_PULLUP);
|
||||||
|
|
||||||
|
// encoder setup
|
||||||
|
palSetPadMode(GPIOB, 12, PAL_MODE_INPUT_PULLUP);
|
||||||
|
palSetPadMode(GPIOB, 13, PAL_MODE_INPUT_PULLUP);
|
||||||
|
|
||||||
|
encoder_state = (palReadPad(GPIOB, 12) << 0) | (palReadPad(GPIOB, 13) << 1);
|
||||||
|
|
||||||
|
// actual matrix setup
|
||||||
|
palSetPadMode(GPIOB, 11, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
palSetPadMode(GPIOB, 10, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
palSetPadMode(GPIOB, 2, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
palSetPadMode(GPIOB, 1, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
palSetPadMode(GPIOA, 7, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
palSetPadMode(GPIOB, 0, PAL_MODE_OUTPUT_PUSHPULL);
|
||||||
|
|
||||||
|
palSetPadMode(GPIOA, 10, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOA, 9, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOA, 8, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOB, 15, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOC, 13, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOC, 14, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOC, 15, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
palSetPadMode(GPIOA, 2, PAL_MODE_INPUT_PULLDOWN);
|
||||||
|
|
||||||
|
|
||||||
|
memset(matrix, 0, MATRIX_ROWS * sizeof(matrix_row_t));
|
||||||
|
memset(matrix_debouncing, 0, MATRIX_COLS * sizeof(matrix_row_t));
|
||||||
|
|
||||||
|
|
||||||
|
matrix_init_quantum();
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void dip_update(uint8_t index, bool active) { }
|
||||||
|
|
||||||
|
__attribute__ ((weak))
|
||||||
|
void encoder_update(bool clockwise) { }
|
||||||
|
|
||||||
|
bool last_dip_switch[4] = {0};
|
||||||
|
|
||||||
|
#ifndef ENCODER_RESOLUTION
|
||||||
|
#define ENCODER_RESOLUTION 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
uint8_t matrix_scan(void) {
|
||||||
|
// dip switch
|
||||||
|
dip_switch[0] = !palReadPad(GPIOB, 14);
|
||||||
|
dip_switch[1] = !palReadPad(GPIOA, 15);
|
||||||
|
dip_switch[2] = !palReadPad(GPIOA, 10);
|
||||||
|
dip_switch[3] = !palReadPad(GPIOB, 9);
|
||||||
|
for (uint8_t i = 0; i < 4; i++) {
|
||||||
|
if (last_dip_switch[i] ^ dip_switch[i])
|
||||||
|
dip_update(i, dip_switch[i]);
|
||||||
|
}
|
||||||
|
memcpy(last_dip_switch, dip_switch, sizeof(&dip_switch));
|
||||||
|
|
||||||
|
// encoder on B12 and B13
|
||||||
|
encoder_state <<= 2;
|
||||||
|
encoder_state |= (palReadPad(GPIOB, 12) << 0) | (palReadPad(GPIOB, 13) << 1);
|
||||||
|
encoder_value += encoder_LUT[encoder_state & 0xF];
|
||||||
|
if (encoder_value >= ENCODER_RESOLUTION) {
|
||||||
|
encoder_update(0);
|
||||||
|
}
|
||||||
|
if (encoder_value <= -ENCODER_RESOLUTION) { // direction is arbitrary here, but this clockwise
|
||||||
|
encoder_update(1);
|
||||||
|
}
|
||||||
|
encoder_value %= ENCODER_RESOLUTION;
|
||||||
|
|
||||||
|
// actual matrix
|
||||||
|
for (int col = 0; col < MATRIX_COLS; col++) {
|
||||||
|
matrix_row_t data = 0;
|
||||||
|
|
||||||
|
// strobe col { B11, B10, B2, B1, A7, B0 }
|
||||||
|
switch (col) {
|
||||||
|
case 0: palSetPad(GPIOB, 11); break;
|
||||||
|
case 1: palSetPad(GPIOB, 10); break;
|
||||||
|
case 2: palSetPad(GPIOB, 2); break;
|
||||||
|
case 3: palSetPad(GPIOB, 1); break;
|
||||||
|
case 4: palSetPad(GPIOA, 7); break;
|
||||||
|
case 5: palSetPad(GPIOB, 0); break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// need wait to settle pin state
|
||||||
|
wait_us(20);
|
||||||
|
|
||||||
|
// read row data { A10, A9, A8, B15, C13, C14, C15, A2 }
|
||||||
|
data = (
|
||||||
|
(palReadPad(GPIOA, 10) << 0 ) |
|
||||||
|
(palReadPad(GPIOA, 9) << 1 ) |
|
||||||
|
(palReadPad(GPIOA, 8) << 2 ) |
|
||||||
|
(palReadPad(GPIOB, 15) << 3 ) |
|
||||||
|
(palReadPad(GPIOC, 13) << 4 ) |
|
||||||
|
(palReadPad(GPIOC, 14) << 5 ) |
|
||||||
|
(palReadPad(GPIOC, 15) << 6 ) |
|
||||||
|
(palReadPad(GPIOA, 2) << 7 )
|
||||||
|
);
|
||||||
|
|
||||||
|
// unstrobe col { B11, B10, B2, B1, A7, B0 }
|
||||||
|
switch (col) {
|
||||||
|
case 0: palClearPad(GPIOB, 11); break;
|
||||||
|
case 1: palClearPad(GPIOB, 10); break;
|
||||||
|
case 2: palClearPad(GPIOB, 2); break;
|
||||||
|
case 3: palClearPad(GPIOB, 1); break;
|
||||||
|
case 4: palClearPad(GPIOA, 7); break;
|
||||||
|
case 5: palClearPad(GPIOB, 0); break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (matrix_debouncing[col] != data) {
|
||||||
|
matrix_debouncing[col] = data;
|
||||||
|
debouncing = true;
|
||||||
|
debouncing_time = timer_read();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (debouncing && timer_elapsed(debouncing_time) > DEBOUNCE) {
|
||||||
|
for (int row = 0; row < MATRIX_ROWS; row++) {
|
||||||
|
matrix[row] = 0;
|
||||||
|
for (int col = 0; col < MATRIX_COLS; col++) {
|
||||||
|
matrix[row] |= ((matrix_debouncing[col] & (1 << row) ? 1 : 0) << col);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
debouncing = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
matrix_scan_quantum();
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool matrix_is_on(uint8_t row, uint8_t col) {
|
||||||
|
return (matrix[row] & (1<<col));
|
||||||
|
}
|
||||||
|
|
||||||
|
matrix_row_t matrix_get_row(uint8_t row) {
|
||||||
|
return matrix[row];
|
||||||
|
}
|
||||||
|
|
||||||
|
void matrix_print(void) {
|
||||||
|
printf("\nr/c 01234567\n");
|
||||||
|
for (uint8_t row = 0; row < MATRIX_ROWS; row++) {
|
||||||
|
printf("%X0: ", row);
|
||||||
|
matrix_row_t data = matrix_get_row(row);
|
||||||
|
for (int col = 0; col < MATRIX_COLS; col++) {
|
||||||
|
if (data & (1<<col))
|
||||||
|
printf("1");
|
||||||
|
else
|
||||||
|
printf("0");
|
||||||
|
}
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
}
|
@ -0,0 +1,257 @@
|
|||||||
|
/*
|
||||||
|
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MCUCONF_H
|
||||||
|
#define MCUCONF_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* STM32F3xx drivers configuration.
|
||||||
|
* The following settings override the default settings present in
|
||||||
|
* the various device driver implementation headers.
|
||||||
|
* Note that the settings for each driver only have effect if the whole
|
||||||
|
* driver is enabled in halconf.h.
|
||||||
|
*
|
||||||
|
* IRQ priorities:
|
||||||
|
* 15...0 Lowest...Highest.
|
||||||
|
*
|
||||||
|
* DMA priorities:
|
||||||
|
* 0...3 Lowest...Highest.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define STM32F3xx_MCUCONF
|
||||||
|
|
||||||
|
/*
|
||||||
|
* HAL driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_NO_INIT FALSE
|
||||||
|
#define STM32_PVD_ENABLE FALSE
|
||||||
|
#define STM32_PLS STM32_PLS_LEV0
|
||||||
|
#define STM32_HSI_ENABLED TRUE
|
||||||
|
#define STM32_LSI_ENABLED TRUE
|
||||||
|
#define STM32_HSE_ENABLED TRUE
|
||||||
|
#define STM32_LSE_ENABLED FALSE
|
||||||
|
#define STM32_SW STM32_SW_PLL
|
||||||
|
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||||
|
#define STM32_PREDIV_VALUE 1
|
||||||
|
#define STM32_PLLMUL_VALUE 9
|
||||||
|
#define STM32_HPRE STM32_HPRE_DIV1
|
||||||
|
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||||
|
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||||
|
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||||
|
#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
|
||||||
|
#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
|
||||||
|
#define STM32_USART1SW STM32_USART1SW_PCLK
|
||||||
|
#define STM32_USART2SW STM32_USART2SW_PCLK
|
||||||
|
#define STM32_USART3SW STM32_USART3SW_PCLK
|
||||||
|
#define STM32_UART4SW STM32_UART4SW_PCLK
|
||||||
|
#define STM32_UART5SW STM32_UART5SW_PCLK
|
||||||
|
#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
|
||||||
|
#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
|
||||||
|
#define STM32_TIM1SW STM32_TIM1SW_PCLK2
|
||||||
|
#define STM32_TIM8SW STM32_TIM8SW_PCLK2
|
||||||
|
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||||
|
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||||
|
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||||
|
|
||||||
|
#undef STM32_HSE_BYPASS
|
||||||
|
// #error "oh no"
|
||||||
|
// #endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ADC driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_ADC_DUAL_MODE FALSE
|
||||||
|
#define STM32_ADC_COMPACT_SAMPLES FALSE
|
||||||
|
#define STM32_ADC_USE_ADC1 FALSE
|
||||||
|
#define STM32_ADC_USE_ADC2 FALSE
|
||||||
|
#define STM32_ADC_USE_ADC3 FALSE
|
||||||
|
#define STM32_ADC_USE_ADC4 FALSE
|
||||||
|
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
|
||||||
|
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
|
||||||
|
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
|
||||||
|
#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
|
||||||
|
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||||
|
#define STM32_ADC_ADC2_DMA_PRIORITY 2
|
||||||
|
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||||
|
#define STM32_ADC_ADC4_DMA_PRIORITY 2
|
||||||
|
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC3_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC4_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
|
||||||
|
#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
|
#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CAN driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_CAN_USE_CAN1 FALSE
|
||||||
|
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DAC driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_DAC_DUAL_MODE FALSE
|
||||||
|
#define STM32_DAC_USE_DAC1_CH1 TRUE
|
||||||
|
#define STM32_DAC_USE_DAC1_CH2 TRUE
|
||||||
|
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
|
||||||
|
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
|
||||||
|
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
|
||||||
|
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* EXT driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
|
||||||
|
#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPT driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_GPT_USE_TIM1 FALSE
|
||||||
|
#define STM32_GPT_USE_TIM2 FALSE
|
||||||
|
#define STM32_GPT_USE_TIM3 FALSE
|
||||||
|
#define STM32_GPT_USE_TIM4 FALSE
|
||||||
|
#define STM32_GPT_USE_TIM6 TRUE
|
||||||
|
#define STM32_GPT_USE_TIM7 TRUE
|
||||||
|
#define STM32_GPT_USE_TIM8 TRUE
|
||||||
|
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
|
||||||
|
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_I2C_USE_I2C1 FALSE
|
||||||
|
#define STM32_I2C_USE_I2C2 FALSE
|
||||||
|
#define STM32_I2C_BUSY_TIMEOUT 50
|
||||||
|
#define STM32_I2C_I2C1_IRQ_PRIORITY 10
|
||||||
|
#define STM32_I2C_I2C2_IRQ_PRIORITY 10
|
||||||
|
#define STM32_I2C_USE_DMA TRUE
|
||||||
|
#define STM32_I2C_I2C1_DMA_PRIORITY 1
|
||||||
|
#define STM32_I2C_I2C2_DMA_PRIORITY 1
|
||||||
|
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ICU driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_ICU_USE_TIM1 FALSE
|
||||||
|
#define STM32_ICU_USE_TIM2 FALSE
|
||||||
|
#define STM32_ICU_USE_TIM3 FALSE
|
||||||
|
#define STM32_ICU_USE_TIM4 FALSE
|
||||||
|
#define STM32_ICU_USE_TIM8 FALSE
|
||||||
|
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||||
|
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||||
|
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||||
|
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||||
|
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PWM driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_PWM_USE_ADVANCED FALSE
|
||||||
|
#define STM32_PWM_USE_TIM1 FALSE
|
||||||
|
#define STM32_PWM_USE_TIM2 FALSE
|
||||||
|
#define STM32_PWM_USE_TIM3 FALSE
|
||||||
|
#define STM32_PWM_USE_TIM4 FALSE
|
||||||
|
#define STM32_PWM_USE_TIM8 FALSE
|
||||||
|
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||||
|
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||||
|
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||||
|
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||||
|
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SERIAL driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_SERIAL_USE_USART1 FALSE
|
||||||
|
#define STM32_SERIAL_USE_USART2 TRUE
|
||||||
|
#define STM32_SERIAL_USE_USART3 FALSE
|
||||||
|
#define STM32_SERIAL_USE_UART4 FALSE
|
||||||
|
#define STM32_SERIAL_USE_UART5 FALSE
|
||||||
|
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||||
|
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||||
|
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||||
|
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||||
|
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPI driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_SPI_USE_SPI1 FALSE
|
||||||
|
#define STM32_SPI_USE_SPI2 FALSE
|
||||||
|
#define STM32_SPI_USE_SPI3 FALSE
|
||||||
|
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||||
|
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||||
|
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||||
|
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||||
|
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||||
|
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||||
|
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ST driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_ST_IRQ_PRIORITY 8
|
||||||
|
#define STM32_ST_USE_TIMER 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_UART_USE_USART1 FALSE
|
||||||
|
#define STM32_UART_USE_USART2 FALSE
|
||||||
|
#define STM32_UART_USE_USART3 FALSE
|
||||||
|
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||||
|
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||||
|
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
|
||||||
|
|
||||||
|
/*
|
||||||
|
* USB driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_USB_USE_USB1 TRUE
|
||||||
|
#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
|
||||||
|
#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
|
||||||
|
#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
|
||||||
|
|
||||||
|
/*
|
||||||
|
* WDG driver system settings.
|
||||||
|
*/
|
||||||
|
#define STM32_WDG_USE_IWDG FALSE
|
||||||
|
|
||||||
|
#endif /* MCUCONF_H */
|
@ -0,0 +1,24 @@
|
|||||||
|
/* Copyright 2018 Jack Humbert <jack.humb@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
#include "rev6.h"
|
||||||
|
|
||||||
|
void matrix_init_kb(void) {
|
||||||
|
matrix_init_user();
|
||||||
|
}
|
||||||
|
|
||||||
|
void matrix_scan_kb(void) {
|
||||||
|
matrix_scan_user();
|
||||||
|
}
|
@ -0,0 +1,21 @@
|
|||||||
|
/* Copyright 2018 Jack Humbert <jack.humb@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
#ifndef REV6_H
|
||||||
|
#define REV6_H
|
||||||
|
|
||||||
|
#include "planck.h"
|
||||||
|
|
||||||
|
#endif
|
@ -0,0 +1,55 @@
|
|||||||
|
# project specific files
|
||||||
|
SRC = matrix.c
|
||||||
|
LAYOUTS += ortho_4x12
|
||||||
|
|
||||||
|
## chip/board settings
|
||||||
|
# - the next two should match the directories in
|
||||||
|
# <chibios>/os/hal/ports/$(MCU_FAMILY)/$(MCU_SERIES)
|
||||||
|
MCU_FAMILY = STM32
|
||||||
|
MCU_SERIES = STM32F3xx
|
||||||
|
|
||||||
|
# Linker script to use
|
||||||
|
# - it should exist either in <chibios>/os/common/ports/ARMCMx/compilers/GCC/ld/
|
||||||
|
# or <this_dir>/ld/
|
||||||
|
MCU_LDSCRIPT = STM32F303xC
|
||||||
|
|
||||||
|
# Startup code to use
|
||||||
|
# - it should exist in <chibios>/os/common/startup/ARMCMx/compilers/GCC/mk/
|
||||||
|
MCU_STARTUP = stm32f3xx
|
||||||
|
|
||||||
|
# Board: it should exist either in <chibios>/os/hal/boards/
|
||||||
|
# or <this_dir>/boards
|
||||||
|
BOARD = GENERIC_STM32_F303XC
|
||||||
|
|
||||||
|
# Cortex version
|
||||||
|
MCU = cortex-m4
|
||||||
|
|
||||||
|
# ARM version, CORTEX-M0/M1 are 6, CORTEX-M3/M4/M7 are 7
|
||||||
|
ARMV = 7
|
||||||
|
|
||||||
|
USE_FPU = yes
|
||||||
|
|
||||||
|
# Vector table for application
|
||||||
|
# 0x00000000-0x00001000 area is occupied by bootlaoder.*/
|
||||||
|
# The CORTEX_VTOR... is needed only for MCHCK/Infinity KB
|
||||||
|
# OPT_DEFS = -DCORTEX_VTOR_INIT=0x08005000
|
||||||
|
OPT_DEFS =
|
||||||
|
|
||||||
|
# Options to pass to dfu-util when flashing
|
||||||
|
DFU_ARGS = -d 0483:df11 -a 0 -s 0x08000000:leave
|
||||||
|
|
||||||
|
# Build Options
|
||||||
|
# comment out to disable the options.
|
||||||
|
#
|
||||||
|
BACKLIGHT_ENABLE = no
|
||||||
|
BOOTMAGIC_ENABLE = yes # Virtual DIP switch configuration
|
||||||
|
## (Note that for BOOTMAGIC on Teensy LC you have to use a custom .ld script.)
|
||||||
|
MOUSEKEY_ENABLE = yes # Mouse keys
|
||||||
|
EXTRAKEY_ENABLE = yes # Audio control and System control
|
||||||
|
CONSOLE_ENABLE = yes # Console for debug
|
||||||
|
COMMAND_ENABLE = yes # Commands for debug and configuration
|
||||||
|
#SLEEP_LED_ENABLE = yes # Breathing sleep LED during USB suspend
|
||||||
|
NKRO_ENABLE = yes # USB Nkey Rollover
|
||||||
|
CUSTOM_MATRIX = yes # Custom matrix file
|
||||||
|
AUDIO_ENABLE = yes
|
||||||
|
# SERIAL_LINK_ENABLE = yes
|
@ -0,0 +1,111 @@
|
|||||||
|
#include "muse.h"
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MUSE_OFF,
|
||||||
|
MUSE_ON,
|
||||||
|
MUSE_C_1_2,
|
||||||
|
MUSE_C1,
|
||||||
|
MUSE_C2,
|
||||||
|
MUSE_C4,
|
||||||
|
MUSE_C8,
|
||||||
|
MUSE_C3,
|
||||||
|
MUSE_C6,
|
||||||
|
MUSE_B1,
|
||||||
|
MUSE_B2,
|
||||||
|
MUSE_B3,
|
||||||
|
MUSE_B4,
|
||||||
|
MUSE_B5,
|
||||||
|
MUSE_B6,
|
||||||
|
MUSE_B7,
|
||||||
|
MUSE_B8,
|
||||||
|
MUSE_B9,
|
||||||
|
MUSE_B10,
|
||||||
|
MUSE_B11,
|
||||||
|
MUSE_B12,
|
||||||
|
MUSE_B13,
|
||||||
|
MUSE_B14,
|
||||||
|
MUSE_B15,
|
||||||
|
MUSE_B16,
|
||||||
|
MUSE_B17,
|
||||||
|
MUSE_B18,
|
||||||
|
MUSE_B19,
|
||||||
|
MUSE_B20,
|
||||||
|
MUSE_B21,
|
||||||
|
MUSE_B22,
|
||||||
|
MUSE_B23,
|
||||||
|
MUSE_B24,
|
||||||
|
MUSE_B25,
|
||||||
|
MUSE_B26,
|
||||||
|
MUSE_B27,
|
||||||
|
MUSE_B28,
|
||||||
|
MUSE_B29,
|
||||||
|
MUSE_B30,
|
||||||
|
MUSE_B31
|
||||||
|
};
|
||||||
|
|
||||||
|
bool number_of_ones_to_bool[16] = {
|
||||||
|
1, 0, 0, 1, 0, 1, 1, 0,
|
||||||
|
0, 1, 1, 0, 1, 0, 0, 1
|
||||||
|
};
|
||||||
|
|
||||||
|
uint8_t muse_interval[4] = {MUSE_B7, MUSE_B19, MUSE_B3, MUSE_B28};
|
||||||
|
uint8_t muse_theme[4] = {MUSE_B8, MUSE_B23, MUSE_B18, MUSE_B17};
|
||||||
|
|
||||||
|
bool muse_timer_1bit = 0;
|
||||||
|
uint8_t muse_timer_2bit = 0;
|
||||||
|
uint8_t muse_timer_2bit_counter = 0;
|
||||||
|
uint8_t muse_timer_4bit = 0;
|
||||||
|
uint32_t muse_timer_31bit = 0;
|
||||||
|
|
||||||
|
bool bit_for_value(uint8_t value) {
|
||||||
|
switch (value) {
|
||||||
|
case MUSE_OFF:
|
||||||
|
return 0;
|
||||||
|
case MUSE_ON:
|
||||||
|
return 1;
|
||||||
|
case MUSE_C_1_2:
|
||||||
|
return muse_timer_1bit;
|
||||||
|
case MUSE_C1:
|
||||||
|
return (muse_timer_4bit & 1);
|
||||||
|
case MUSE_C2:
|
||||||
|
return (muse_timer_4bit & 2);
|
||||||
|
case MUSE_C4:
|
||||||
|
return (muse_timer_4bit & 4);
|
||||||
|
case MUSE_C8:
|
||||||
|
return (muse_timer_4bit & 8);
|
||||||
|
case MUSE_C3:
|
||||||
|
return (muse_timer_2bit & 1);
|
||||||
|
case MUSE_C6:
|
||||||
|
return (muse_timer_2bit & 2);
|
||||||
|
default:
|
||||||
|
return muse_timer_31bit & (1UL << (value - MUSE_B1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t muse_clock_pulse(void) {
|
||||||
|
|
||||||
|
bool top = number_of_ones_to_bool[
|
||||||
|
bit_for_value(muse_theme[0]) +
|
||||||
|
(bit_for_value(muse_theme[1]) << 1) +
|
||||||
|
(bit_for_value(muse_theme[2]) << 2) +
|
||||||
|
(bit_for_value(muse_theme[3]) << 3)
|
||||||
|
];
|
||||||
|
|
||||||
|
if (muse_timer_1bit == 0) {
|
||||||
|
if (muse_timer_2bit_counter == 0) {
|
||||||
|
muse_timer_2bit = (muse_timer_2bit + 1) % 4;
|
||||||
|
}
|
||||||
|
muse_timer_2bit_counter = (muse_timer_2bit_counter + 1) % 3;
|
||||||
|
muse_timer_4bit = (muse_timer_4bit + 1) % 16;
|
||||||
|
muse_timer_31bit = (muse_timer_31bit << 1) + top;
|
||||||
|
}
|
||||||
|
|
||||||
|
muse_timer_1bit = (muse_timer_1bit + 1) % 2;
|
||||||
|
|
||||||
|
return
|
||||||
|
bit_for_value(muse_interval[0]) +
|
||||||
|
(bit_for_value(muse_interval[1]) << 1) +
|
||||||
|
(bit_for_value(muse_interval[2]) << 2) +
|
||||||
|
(bit_for_value(muse_interval[3]) << 3);
|
||||||
|
|
||||||
|
}
|
@ -0,0 +1,9 @@
|
|||||||
|
#ifndef MUSE_H
|
||||||
|
#define MUSE_H
|
||||||
|
|
||||||
|
#include "quantum.h"
|
||||||
|
#include "process_audio.h"
|
||||||
|
|
||||||
|
uint8_t muse_clock_pulse(void);
|
||||||
|
|
||||||
|
#endif
|
Loading…
Reference in New Issue