You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
300 lines
14 KiB
C
300 lines
14 KiB
C
/*
|
|
** ###################################################################
|
|
** Compilers: ARM Compiler
|
|
** Freescale C/C++ for Embedded ARM
|
|
** GNU C Compiler
|
|
** IAR ANSI C/C++ Compiler for ARM
|
|
**
|
|
** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
|
|
** K20P32M50SF0RM Rev. 1, Oct 2011
|
|
** K20P48M50SF0RM Rev. 1, Oct 2011
|
|
**
|
|
** Version: rev. 1.0, 2011-12-15
|
|
**
|
|
** Abstract:
|
|
** Provides a system configuration function and a global variable that
|
|
** contains the system frequency. It configures the device and initializes
|
|
** the oscillator (PLL) that is part of the microcontroller device.
|
|
**
|
|
** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
|
**
|
|
** http: www.freescale.com
|
|
** mail: support@freescale.com
|
|
**
|
|
** Revisions:
|
|
** - rev. 1.0 (2011-12-15)
|
|
** Initial version
|
|
**
|
|
** ###################################################################
|
|
*/
|
|
|
|
/**
|
|
* @file MK20D5
|
|
* @version 1.0
|
|
* @date 2011-12-15
|
|
* @brief Device specific configuration file for MK20D5 (implementation file)
|
|
*
|
|
* Provides a system configuration function and a global variable that contains
|
|
* the system frequency. It configures the device and initializes the oscillator
|
|
* (PLL) that is part of the microcontroller device.
|
|
*/
|
|
|
|
#include <stdint.h>
|
|
#include "MK20D5.h"
|
|
|
|
#define DISABLE_WDOG 1
|
|
|
|
#define CLOCK_SETUP 3
|
|
/* Predefined clock setups
|
|
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
|
|
Reference clock source for MCG module is the slow internal clock source 32.768kHz
|
|
Core clock = 41.94MHz, BusClock = 41.94MHz
|
|
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
|
|
Reference clock source for MCG module is an external crystal 8MHz
|
|
Core clock = 48MHz, BusClock = 48MHz
|
|
2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
|
|
Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
|
|
Core clock = 8MHz, BusClock = 8MHz
|
|
*/
|
|
|
|
/*----------------------------------------------------------------------------
|
|
Define clock source values
|
|
*----------------------------------------------------------------------------*/
|
|
#if (CLOCK_SETUP == 0)
|
|
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
|
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
|
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
|
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
|
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
|
|
#elif (CLOCK_SETUP == 1)
|
|
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
|
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
|
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
|
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
|
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
|
#elif (CLOCK_SETUP == 2)
|
|
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
|
|
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
|
|
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
|
|
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
|
#define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
|
|
#elif (CLOCK_SETUP == 3)
|
|
/* for Infinity */
|
|
#define CPU_XTAL_CLK_HZ 8000000u
|
|
#define CPU_XTAL32k_CLK_HZ 32768u
|
|
#define CPU_INT_SLOW_CLK_HZ 32768u
|
|
#define CPU_INT_FAST_CLK_HZ 4000000u
|
|
#define DEFAULT_SYSTEM_CLOCK 48000000u
|
|
#endif
|
|
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- Core clock
|
|
---------------------------------------------------------------------------- */
|
|
|
|
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SystemInit()
|
|
---------------------------------------------------------------------------- */
|
|
|
|
void SystemInit (void) {
|
|
#if (DISABLE_WDOG)
|
|
/* Disable the WDOG module */
|
|
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
|
|
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
|
|
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
|
|
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
|
|
/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
|
|
WDOG->STCTRLH = (uint16_t)0x01D2u;
|
|
#endif /* (DISABLE_WDOG) */
|
|
#if (CLOCK_SETUP == 0)
|
|
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
|
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
|
/* Switch to FEI Mode */
|
|
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG->C1 = (uint8_t)0x06u;
|
|
/* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
|
|
MCG->C2 = (uint8_t)0x00u;
|
|
/* MCG_C4: DMX32=0,DRST_DRS=1 */
|
|
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
|
|
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
|
|
MCG->C5 = (uint8_t)0x00u;
|
|
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
|
|
MCG->C6 = (uint8_t)0x00u;
|
|
while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
|
}
|
|
while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
|
|
}
|
|
#elif (CLOCK_SETUP == 1)
|
|
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
|
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
|
/* Switch to FBE Mode */
|
|
/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
|
OSC0->CR = (uint8_t)0x00u;
|
|
/* MCG->C7: OSCSEL=0 */
|
|
MCG->C7 = (uint8_t)0x00u;
|
|
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
|
MCG->C2 = (uint8_t)0x24u;
|
|
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG->C1 = (uint8_t)0x9Au;
|
|
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
|
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
|
|
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
|
|
MCG->C5 = (uint8_t)0x03u;
|
|
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
|
|
MCG->C6 = (uint8_t)0x00u;
|
|
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
|
|
}
|
|
#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
|
|
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
|
}
|
|
#endif
|
|
while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
|
|
}
|
|
/* Switch to PBE Mode */
|
|
/* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
|
|
MCG->C5 = (uint8_t)0x03u;
|
|
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
|
|
MCG->C6 = (uint8_t)0x40u;
|
|
while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
|
|
}
|
|
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
|
|
}
|
|
/* Switch to PEE Mode */
|
|
/* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG->C1 = (uint8_t)0x1Au;
|
|
while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
|
|
}
|
|
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
|
|
}
|
|
#elif (CLOCK_SETUP == 2)
|
|
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
|
|
SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
|
|
/* Switch to FBE Mode */
|
|
/* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
|
OSC0->CR = (uint8_t)0x00u;
|
|
/* MCG->C7: OSCSEL=0 */
|
|
MCG->C7 = (uint8_t)0x00u;
|
|
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
|
MCG->C2 = (uint8_t)0x24u;
|
|
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
|
MCG->C1 = (uint8_t)0x9Au;
|
|
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
|
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
|
|
/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
|
|
MCG->C5 = (uint8_t)0x00u;
|
|
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
|
|
MCG->C6 = (uint8_t)0x00u;
|
|
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
|
|
}
|
|
#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
|
|
while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
|
}
|
|
#endif
|
|
while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
|
|
}
|
|
/* Switch to BLPE Mode */
|
|
/* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
|
|
MCG->C2 = (uint8_t)0x24u;
|
|
|
|
#elif (CLOCK_SETUP == 3)
|
|
/* for Infinity FEI: 48MHz */
|
|
|
|
/* OUTDIV1(core/system): 48/1, OUTDIV2(bus): 48/1, OUTDIV4(flash): 48/2 */
|
|
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1);
|
|
MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
|
|
/* 32.768KHz x FLL(1464) = 48MHz */
|
|
MCG->C4 = MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(1);
|
|
/* USB clock source: MCGPLLCLK/MCGFLLCLK */
|
|
//SIM->SOPT2 = SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_TRACECLKSEL_MASK;
|
|
|
|
while((MCG->S & MCG_S_IREFST_MASK) == 0u) { }
|
|
while((MCG->S & 0x0Cu) != 0x00u) { }
|
|
#endif
|
|
}
|
|
|
|
/* ----------------------------------------------------------------------------
|
|
-- SystemCoreClockUpdate()
|
|
---------------------------------------------------------------------------- */
|
|
|
|
void SystemCoreClockUpdate (void) {
|
|
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
|
uint8_t Divider;
|
|
|
|
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
|
/* Output of FLL or PLL is selected */
|
|
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
|
|
/* FLL is selected */
|
|
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
|
/* External reference clock is selected */
|
|
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
|
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
|
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
|
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
|
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
|
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
|
|
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
|
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
|
|
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
|
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
|
/* Select correct multiplier to calculate the MCG output clock */
|
|
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
|
case 0x0u:
|
|
MCGOUTClock *= 640u;
|
|
break;
|
|
case 0x20u:
|
|
MCGOUTClock *= 1280u;
|
|
break;
|
|
case 0x40u:
|
|
MCGOUTClock *= 1920u;
|
|
break;
|
|
case 0x60u:
|
|
MCGOUTClock *= 2560u;
|
|
break;
|
|
case 0x80u:
|
|
MCGOUTClock *= 732u;
|
|
break;
|
|
case 0xA0u:
|
|
MCGOUTClock *= 1464u;
|
|
break;
|
|
case 0xC0u:
|
|
MCGOUTClock *= 2197u;
|
|
break;
|
|
case 0xE0u:
|
|
MCGOUTClock *= 2929u;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
|
/* PLL is selected */
|
|
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
|
|
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
|
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
|
|
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
|
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
|
/* Internal reference clock is selected */
|
|
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
|
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
|
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
|
|
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
|
/* External reference clock is selected */
|
|
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
|
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
|
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
|
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
|
/* Reserved value */
|
|
return;
|
|
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
|
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
|
}
|