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469 lines
18 KiB
C
469 lines
18 KiB
C
8 years ago
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/*
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LUFA Library
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Copyright (C) Dean Camera, 2017.
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dean [at] fourwalledcubicle [dot] com
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www.lufa-lib.org
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*/
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/*
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Copyright 2017 Dean Camera (dean [at] fourwalledcubicle [dot] com)
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Permission to use, copy, modify, distribute, and sell this
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software and its documentation for any purpose is hereby granted
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without fee, provided that the above copyright notice appear in
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all copies and that both that the copyright notice and this
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permission notice and warranty disclaimer appear in supporting
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documentation, and that the name of the author not be used in
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advertising or publicity pertaining to distribution of the
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software without specific, written prior permission.
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The author disclaims all warranties with regard to this
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software, including all implied warranties of merchantability
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and fitness. In no event shall the author be liable for any
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special, indirect or consequential damages or any damages
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whatsoever resulting from loss of use, data or profits, whether
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in an action of contract, negligence or other tortious action,
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arising out of or in connection with the use or performance of
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this software.
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*/
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/** \file
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*
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* Target-related functions for the XMEGA target's NVM module.
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*/
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#define INCLUDE_FROM_XMEGA_NVM_C
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#include "XMEGANVM.h"
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#if defined(ENABLE_XPROG_PROTOCOL) || defined(__DOXYGEN__)
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/** Sends the given 32-bit absolute address to the target.
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*
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* \param[in] AbsoluteAddress Absolute address to send to the target
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*/
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static void XMEGANVM_SendAddress(const uint32_t AbsoluteAddress)
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{
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/* Send the given 32-bit address to the target, LSB first */
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XPROGTarget_SendByte(AbsoluteAddress & 0xFF);
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XPROGTarget_SendByte(AbsoluteAddress >> 8);
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XPROGTarget_SendByte(AbsoluteAddress >> 16);
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XPROGTarget_SendByte(AbsoluteAddress >> 24);
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}
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/** Sends the given NVM register address to the target.
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*
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* \param[in] Register NVM register whose absolute address is to be sent
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*/
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static void XMEGANVM_SendNVMRegAddress(const uint8_t Register)
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{
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/* Determine the absolute register address from the NVM base memory address and the NVM register address */
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uint32_t Address = XPROG_Param_NVMBase | Register;
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/* Send the calculated 32-bit address to the target, LSB first */
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XMEGANVM_SendAddress(Address);
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}
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/** Busy-waits while the NVM controller is busy performing a NVM operation, such as a FLASH page read or CRC
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* calculation.
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*
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* \return Boolean \c true if the NVM controller became ready within the timeout period, \c false otherwise
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*/
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bool XMEGANVM_WaitWhileNVMBusBusy(void)
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{
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/* Poll the STATUS register to check to see if NVM access has been enabled */
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for (;;)
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{
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/* Send the LDCS command to read the PDI STATUS register to see the NVM bus is active */
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XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_STATUS));
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uint8_t StatusRegister = XPROGTarget_ReceiveByte();
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/* We might have timed out waiting for the status register read response, check here */
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if (!(TimeoutTicksRemaining))
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return false;
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/* Check the status register read response to see if the NVM bus is enabled */
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if (StatusRegister & PDI_STATUS_NVM)
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return true;
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}
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}
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/** Waits while the target's NVM controller is busy performing an operation, exiting if the
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* timeout period expires.
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*
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* \return Boolean \c true if the NVM controller became ready within the timeout period, \c false otherwise
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*/
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bool XMEGANVM_WaitWhileNVMControllerBusy(void)
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{
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/* Preload the pointer register with the NVM STATUS register address to check the BUSY flag */
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_STATUS);
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/* Poll the NVM STATUS register while the NVM controller is busy */
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for (;;)
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{
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/* Fetch the current status value via the pointer register (without auto-increment afterwards) */
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT, PDI_DATASIZE_1BYTE));
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uint8_t StatusRegister = XPROGTarget_ReceiveByte();
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/* We might have timed out waiting for the status register read response, check here */
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if (!(TimeoutTicksRemaining))
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return false;
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/* Check to see if the BUSY flag is still set */
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if (!(StatusRegister & (1 << 7)))
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return true;
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}
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}
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/** Enables the physical PDI interface on the target and enables access to the internal NVM controller.
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*
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* \return Boolean \c true if the PDI interface was enabled successfully, \c false otherwise
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*/
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bool XMEGANVM_EnablePDI(void)
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{
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/* Enable PDI programming mode with the attached target */
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XPROGTarget_EnableTargetPDI();
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/* Store the RESET key into the RESET PDI register to keep the XMEGA in reset */
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET));
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XPROGTarget_SendByte(PDI_RESET_KEY);
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/* Lower direction change guard time to 32 USART bits */
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_CTRL));
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XPROGTarget_SendByte(0x02);
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/* Enable access to the XPROG NVM bus by sending the documented NVM access key to the device */
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XPROGTarget_SendByte(PDI_CMD_KEY);
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for (uint8_t i = sizeof(PDI_NVMENABLE_KEY); i > 0; i--)
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XPROGTarget_SendByte(PDI_NVMENABLE_KEY[i - 1]);
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/* Wait until the NVM bus becomes active */
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return XMEGANVM_WaitWhileNVMBusBusy();
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}
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/** Removes access to the target's NVM controller and physically disables the target's physical PDI interface. */
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void XMEGANVM_DisablePDI(void)
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{
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XMEGANVM_WaitWhileNVMBusBusy();
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/* Clear the RESET key in the RESET PDI register to allow the XMEGA to run - must perform this until the
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* change takes effect, as in some cases it takes multiple writes (silicon bug?).
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*/
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do
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{
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/* Clear reset register */
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XPROGTarget_SendByte(PDI_CMD_STCS(PDI_REG_RESET));
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XPROGTarget_SendByte(0x00);
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/* Read back the reset register, check to see if it took effect */
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XPROGTarget_SendByte(PDI_CMD_LDCS(PDI_REG_RESET));
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} while (XPROGTarget_ReceiveByte() != 0x00);
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XPROGTarget_DisableTargetPDI();
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}
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/** Retrieves the CRC value of the given memory space.
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*
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* \param[in] CRCCommand NVM CRC command to issue to the target
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* \param[out] CRCDest CRC Destination when read from the target
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*
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* \return Boolean \c true if the command sequence complete successfully
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*/
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bool XMEGANVM_GetMemoryCRC(const uint8_t CRCCommand,
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uint32_t* const CRCDest)
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{
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*CRCDest = 0;
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Set the NVM command to the correct CRC read command */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(CRCCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the CRC generation */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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/* Wait until the NVM bus is ready again */
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if (!(XMEGANVM_WaitWhileNVMBusBusy()))
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return false;
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Load the PDI pointer register with the DAT0 register start address */
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_DAT0);
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/* Send the REPEAT command to grab the CRC bytes */
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XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE));
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XPROGTarget_SendByte(XMEGA_CRC_LENGTH_BYTES - 1);
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/* Read in the CRC bytes from the target */
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE));
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for (uint8_t i = 0; i < XMEGA_CRC_LENGTH_BYTES; i++)
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((uint8_t*)CRCDest)[i] = XPROGTarget_ReceiveByte();
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return (TimeoutTicksRemaining > 0);
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}
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/** Reads memory from the target's memory spaces.
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*
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* \param[in] ReadAddress Start address to read from within the target's address space
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* \param[out] ReadBuffer Buffer to store read data into
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* \param[in] ReadSize Number of bytes to read
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*
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* \return Boolean \c true if the command sequence complete successfully
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*/
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bool XMEGANVM_ReadMemory(const uint32_t ReadAddress,
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uint8_t* ReadBuffer,
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uint16_t ReadSize)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the READNVM command to the NVM controller for reading of an arbitrary location */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(XMEGA_NVM_CMD_READNVM);
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if (ReadSize > 1)
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{
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/* Load the PDI pointer register with the start address we want to read from */
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XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES));
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XMEGANVM_SendAddress(ReadAddress);
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/* Send the REPEAT command with the specified number of bytes to read */
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XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE));
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XPROGTarget_SendByte(ReadSize - 1);
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/* Send a LD command with indirect access and post-increment to read out the bytes */
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XPROGTarget_SendByte(PDI_CMD_LD(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE));
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while (ReadSize-- && TimeoutTicksRemaining)
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*(ReadBuffer++) = XPROGTarget_ReceiveByte();
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}
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else
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{
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/* Send a LDS command with the read address to read out the requested byte */
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XPROGTarget_SendByte(PDI_CMD_LDS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendAddress(ReadAddress);
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*(ReadBuffer++) = XPROGTarget_ReceiveByte();
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}
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return (TimeoutTicksRemaining > 0);
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}
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/** Writes byte addressed memory to the target's memory spaces.
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*
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* \param[in] WriteCommand Command to send to the device to write each memory byte
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* \param[in] WriteAddress Address to write to within the target's address space
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* \param[in] Byte Byte to write to the target
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*
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* \return Boolean \c true if the command sequence complete successfully
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*/
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bool XMEGANVM_WriteByteMemory(const uint8_t WriteCommand,
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const uint32_t WriteAddress,
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const uint8_t Byte)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(WriteCommand);
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/* Send new memory byte to the memory of the target */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendAddress(WriteAddress);
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XPROGTarget_SendByte(Byte);
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return true;
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}
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/** Writes page addressed memory to the target's memory spaces.
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*
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* \param[in] WriteBuffCommand Command to send to the device to write a byte to the memory page buffer
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* \param[in] EraseBuffCommand Command to send to the device to erase the memory page buffer
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* \param[in] WritePageCommand Command to send to the device to write the page buffer to the destination memory
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* \param[in] PageMode Bitfield indicating what operations need to be executed on the specified page
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* \param[in] WriteAddress Start address to write the page data to within the target's address space
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* \param[in] WriteBuffer Buffer to source data from
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* \param[in] WriteSize Number of bytes to write
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*
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* \return Boolean \c true if the command sequence complete successfully
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*/
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bool XMEGANVM_WritePageMemory(const uint8_t WriteBuffCommand,
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const uint8_t EraseBuffCommand,
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const uint8_t WritePageCommand,
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const uint8_t PageMode,
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const uint32_t WriteAddress,
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const uint8_t* WriteBuffer,
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uint16_t WriteSize)
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{
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if (PageMode & XPROG_PAGEMODE_ERASE)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory buffer erase command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
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XPROGTarget_SendByte(EraseBuffCommand);
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/* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
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XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
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XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
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}
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if (WriteSize)
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{
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/* Wait until the NVM controller is no longer busy */
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if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
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return false;
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/* Send the memory buffer write command to the target */
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XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(WriteBuffCommand);
|
||
|
|
|
||
|
|
/* Load the PDI pointer register with the start address we want to write to */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES));
|
||
|
|
XMEGANVM_SendAddress(WriteAddress);
|
||
|
|
|
||
|
|
/* Send the REPEAT command with the specified number of bytes to write */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE));
|
||
|
|
XPROGTarget_SendByte(WriteSize - 1);
|
||
|
|
|
||
|
|
/* Send a ST command with indirect access and post-increment to write the bytes */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE));
|
||
|
|
while (WriteSize--)
|
||
|
|
XPROGTarget_SendByte(*(WriteBuffer++));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (PageMode & XPROG_PAGEMODE_WRITE)
|
||
|
|
{
|
||
|
|
/* Wait until the NVM controller is no longer busy */
|
||
|
|
if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
/* Send the memory write command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(WritePageCommand);
|
||
|
|
|
||
|
|
/* Send the address of the first page location to write the memory page */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendAddress(WriteAddress);
|
||
|
|
XPROGTarget_SendByte(0x00);
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Erases a specific memory space of the target.
|
||
|
|
*
|
||
|
|
* \param[in] EraseCommand NVM erase command to send to the device
|
||
|
|
* \param[in] Address Address inside the memory space to erase
|
||
|
|
*
|
||
|
|
* \return Boolean \c true if the command sequence complete successfully
|
||
|
|
*/
|
||
|
|
bool XMEGANVM_EraseMemory(const uint8_t EraseCommand,
|
||
|
|
const uint32_t Address)
|
||
|
|
{
|
||
|
|
/* Wait until the NVM controller is no longer busy */
|
||
|
|
if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
/* EEPROM and Chip erasures are triggered differently to FLASH section erasures */
|
||
|
|
if (EraseCommand == XMEGA_NVM_CMD_CHIPERASE)
|
||
|
|
{
|
||
|
|
/* Send the memory erase command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(EraseCommand);
|
||
|
|
|
||
|
|
/* Set CMDEX bit in NVM CTRLA register to start the erase sequence */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
|
||
|
|
XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
|
||
|
|
}
|
||
|
|
else if (EraseCommand == XMEGA_NVM_CMD_ERASEEEPROM)
|
||
|
|
{
|
||
|
|
/* Send the EEPROM page buffer erase command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(XMEGA_NVM_CMD_ERASEEEPROMPAGEBUFF);
|
||
|
|
|
||
|
|
/* Set CMDEX bit in NVM CTRLA register to start the buffer erase */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
|
||
|
|
XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
|
||
|
|
|
||
|
|
/* Wait until the NVM controller is no longer busy */
|
||
|
|
if (!(XMEGANVM_WaitWhileNVMControllerBusy()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
/* Send the EEPROM memory buffer write command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(XMEGA_NVM_CMD_LOADEEPROMPAGEBUFF);
|
||
|
|
|
||
|
|
/* Load the PDI pointer register with the EEPROM page start address */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_DIRECT, PDI_DATASIZE_4BYTES));
|
||
|
|
XMEGANVM_SendAddress(Address);
|
||
|
|
|
||
|
|
/* Send the REPEAT command with the specified number of bytes to write */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_REPEAT(PDI_DATASIZE_1BYTE));
|
||
|
|
XPROGTarget_SendByte(XPROG_Param_EEPageSize - 1);
|
||
|
|
|
||
|
|
/* Send a ST command with indirect access and post-increment to tag each byte in the EEPROM page buffer */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_ST(PDI_POINTER_INDIRECT_PI, PDI_DATASIZE_1BYTE));
|
||
|
|
for (uint8_t PageByte = 0; PageByte < XPROG_Param_EEPageSize; PageByte++)
|
||
|
|
XPROGTarget_SendByte(0x00);
|
||
|
|
|
||
|
|
/* Send the memory erase command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(EraseCommand);
|
||
|
|
|
||
|
|
/* Set CMDEX bit in NVM CTRLA register to start the EEPROM erase sequence */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CTRLA);
|
||
|
|
XPROGTarget_SendByte(XMEGA_NVM_BIT_CTRLA_CMDEX);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Send the memory erase command to the target */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendNVMRegAddress(XMEGA_NVM_REG_CMD);
|
||
|
|
XPROGTarget_SendByte(EraseCommand);
|
||
|
|
|
||
|
|
/* Other erase modes just need us to address a byte within the target memory space */
|
||
|
|
XPROGTarget_SendByte(PDI_CMD_STS(PDI_DATASIZE_4BYTES, PDI_DATASIZE_1BYTE));
|
||
|
|
XMEGANVM_SendAddress(Address);
|
||
|
|
XPROGTarget_SendByte(0x00);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Wait until the NVM bus is ready again */
|
||
|
|
if (!(XMEGANVM_WaitWhileNVMBusBusy()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|